IEICE Transactions on Electronics
Online ISSN : 1745-1353
Print ISSN : 0916-8524
Regular Section
A Low Jitter Self-Calibration PLL for 10-Gbps SoC Transmission Links Application
Kuo-Hsing CHENGYu-Chang TSAIChien-Nan Jimmy LIUKai-Wei HONGChin-Cheng KUO
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2009 Volume E92.C Issue 7 Pages 964-972

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Abstract

A 2.5GHz 8-phase phase-locked loop (PLL) is proposed for 10-Gbps system on chip (SoC) transmission links application. The proposed PLL has several features which use new design techniques. The first one is a new variable delay cell (VDC) for the voltage control oscillator (VCO). Its advantages over the conventional delay cell are: wide-range output frequency and low noise sensitivity with low KVCO. The second feature is that, the PLL consists of a self-calibration circuit (SCC) which protects the PLL from variations in the process, voltage and temperature (PVT). The third feature is that, the proposed PLL has an 8-phase output frequency and also for avoiding the power/ground (P/G) effect and the substrate noise effect on the PLL, it also has a low jitter output frequency. The PLL is implemented in 0.13-µm CMOS technology. The PLL output jitter is 2.83ps (rms) less than 0.7% of the output period. The total power dissipation is 21mW at 2.5GHz output frequency, and the core area is 0.08mm2.

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© 2009 The Institute of Electronics, Information and Communication Engineers
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