In order to explore the feasibility of large-scale subthreshold logic circuits and to clarify the lower limit of supply voltage (V_DD) for logic circuits, the dependence of the minimum operating voltage (V_DDmin) of CMOS logic gates on the number of stages, gate types and gate width is systematically measured with 90nm CMOS ring oscillators (RO's). The measured average V_DDmin of inverter RO's increased from 90mV to 343mV when the number of RO stages increased from 11 to 1Mega, which indicates the difficulty of V_DD scaling in large-scale subthreshold logic circuits. The dependence of V_DDmin on the number of stages is calculated using the subthreshold current model with random threshold voltage (V_TH) variations and compared with the measured results, and the tendency of the measurement is confirmed. The effect of adaptive body bias control to compensate purely random V_TH variation is also investigated. Such compensation would require impractical inverter-by-inverter adaptive body bias control.