IEICE Transactions on Electronics
Online ISSN : 1745-1353
Print ISSN : 0916-8524
Special Section on Circuits and Design Techniques for Advanced Large Scale Integration
Impact of Self-Heating in Wire Interconnection on Timing
Toshiki KANAMOTO, Takaaki OKUMURA, Katsuhiro FURUKAWA, Hiroshi TAKAFUJI, Atsushi KUROKAWA, Koutaro HACHIYA, Tsuyoshi SAKATA, Masakazu TANAKA, Hidenari NAKASHIMA, Hiroo MASUDA, Takashi SATO, Masanori HASHIMOTO
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Keywords: interconnect, delay variation, parasitic resistance, thermal, temperature, self-heat, SoC
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2010 Volume E93.C Issue 3 Pages 388-392

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Abstract

This paper evaluates impact of self-heating in wire interconnection on signal propagation delay in an upcoming 32nm process technology, using practical physical parameters. This paper examines a 64-bit data transmission model as one of the most heating cases. Experimental results show that the maximum wire temperature increase due to the self-heating appears in the case where the ratio of interconnect delay becomes largest compared to the driver delay. However, even in the most significant case which induces the maximum temperature rise of 11.0°C, the corresponding increase in the wire resistance is 1.99% and the resulting delay increase is only 1.15%, as for the assumed 32nm process. A part of the impact reduction of wire self-heating on timing comes from the size-effect of nano-scale wires.

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© 2010 The Institute of Electronics, Information and Communication Engineers
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