Boosted Bit Line Program Scheme for Low Operating Voltage MLC NAND Flash Memory

Youngsun SONG; Ki-Tae PARK; Myounggon KANG; Yunheub SONG; Sungsoo LEE; Youngho LIM; Kang-Deog SUH

doi:10.1587/transele.E93.C.423

Regular Section

Boosted Bit Line Program Scheme for Low Operating Voltage MLC NAND Flash Memory

Youngsun SONG, Ki-Tae PARK, Myounggon KANG, Yunheub SONG, Sungsoo LEE, Youngho LIM, Kang-Deog SUH

Author information

Keywords: bit line, coupling capacitance, V_pass window margin, boosted channel

JOURNAL RESTRICTED ACCESS

2010 Volume E93.C Issue 3 Pages 423-425

DOI https://doi.org/10.1587/transele.E93.C.423

Details

Abstract

A boosted bit line program scheme is proposed for low operating voltage in the multi-level-cell (MLC) NAND flash memory. Our BL to BL boosting scheme, which uses the BL coupling capacitance, is applied to achieve a higher channel potential than is possible with V_cc, so that the V_pass window margin is improved by up to 59% in 40nm MLC NAND flash memory with 2.7V V_cc. In the case of 1.8V V_cc, the margin of the proposed scheme is 12% higher than one of the conventional schemes at 2.7V V_cc.

Corresponding author

Register with J-STAGE for free!