IEICE Transactions on Electronics
Online ISSN : 1745-1353
Print ISSN : 0916-8524
Regular Section
Design Methodologies for STT-MRAM (Spin-Torque Transfer Magnetic Random Access Memory) Sensing Circuits
Jisu KIMJee-Hwan SONGSeung-Hyuk KANGSei-Seung YOONSeong-Ook JUNG
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2010 Volume E93.C Issue 6 Pages 912-921

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Abstract

Spin-torque transfer magnetic random access memory (STT-MRAM) is a promising technology for next generation nonvolatile universal memory because it reduces the high write current required by conventional MRAM and enables write current scaling as technology becomes smaller in size. However, the sensing margin is not improved in STT-MRAM and tends to decrease with technology scaling due to the lowered supply voltage and increased process variation. Moreover, read disturbance, which is an unwanted write in a read operation, can occur in STT-MRAM because its read and write operations use the same path. To overcome these problems, we present a load-line analysis method, which is useful for systematically analyzing the impacts of transistor size and gate voltage of MOSFETs on the sensing margin, and also propose an optimization procedure for the commonly applicable MRAM sensing circuits. This methodology constitutes an effective means to optimize the transistor size and gate voltage of MOSFETs and thus maximizes the sensing margin without causing read disturbance.

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© 2010 The Institute of Electronics, Information and Communication Engineers
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