Regular Section
Design and Performance of a Sub-Nano-Ampere Two-Stage Power Management Circuit in 0.35-µm CMOS for Dust-Size Sensor Nodes
2011 Volume E94.C Issue 7 Pages 1206-1211
Details
2011 Volume E94.C Issue 7 Pages 1206-1211
The design and performance of a sub-nanoampere two-stage power management circuit that uses off-chip capacitors for energy accumulation are presented. Focusing on the leakage current and the transition time of the power switch transistor, we estimated the minimum current for accumulating. On the basis of the results, we devised a two-stage power management architecture for sub-nanoampere operation. The simulated and experimental results for the power management circuit describe the accumulating operation with a 1-nA current source.
