High Throughput Parallel Arithmetic Circuits for Fast Fourier Transform

Ryosuke NAKAMOTO; Sakae SAKURABA; Alexandre MARTINS; Takeshi ONOMI; Shigeo SATO; Koji NAKAJIMA

doi:10.1587/transele.E94.C.280

Special Section on Superconducting Signal Processing Technologies

High Throughput Parallel Arithmetic Circuits for Fast Fourier Transform

Ryosuke NAKAMOTO, Sakae SAKURABA, Alexandre MARTINS, Takeshi ONOMI, Shigeo SATO, Koji NAKAJIMA

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Keywords: SFQ, super-conductive circuits, FFT, multiplier, adder

JOURNAL RESTRICTED ACCESS

2011 Volume E94.C Issue 3 Pages 280-287

DOI https://doi.org/10.1587/transele.E94.C.280

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Abstract

We have designed and implemented a 4-bit Carry Look-ahead Adder (CLA) and 4-bit parallel multipliers to be used for the Fast Fourier Transform (FFT) system with the estimated clock frequency of 20GHz. Through some high frequency functional tests, we have confirmed that the operation of the CLA has been successful. Through some low speed tests, we have also confirmed that the operation of multiplication has been successful. In addition, we have designed a 4-bit multiplier with a Booth encoder and with a 2-point-4-bit butterfly circuit.

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