0.5-V Input Digital Low-Dropout Regulator (LDO) with 98.7% Current Efficiency in 65nm CMOS

Yasuyuki OKUMA; Koichi ISHIDA; Yoshikatsu RYU; Xin ZHANG; Po-Hung CHEN; Kazunori WATANABE; Makoto TAKAMIYA; Takayasu SAKURAI

doi:10.1587/transele.E94.C.938

Special Section on Analog Circuits and Related SoC Integration Technologies

0.5-V Input Digital Low-Dropout Regulator (LDO) with 98.7% Current Efficiency in 65nm CMOS

Yasuyuki OKUMA, Koichi ISHIDA, Yoshikatsu RYU, Xin ZHANG, Po-Hung CHEN, Kazunori WATANABE, Makoto TAKAMIYA, Takayasu SAKURAI

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Keywords: low dropout regulator, digital control, low voltage

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2011 Volume E94.C Issue 6 Pages 938-944

DOI https://doi.org/10.1587/transele.E94.C.938

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Abstract

In this paper, Digital Low Dropout Regulator (LDO) is proposed to provide the low noise and tunable power supply voltage to the 0.5-V near-threshold logic circuits. Because the conventional LDO feedback-controlled by the operational amplifier fail to operate at 0.5V, the digital LDO eliminates all analog circuits and is controlled by digital circuits, which enables the 0.5-V operation. The developed digital LDO in 65nm CMOS achieved the 0.5-V input voltage and 0.45-V output voltage with 98.7% current efficiency and 2.7-µA quiescent current at 200-µA load current. Both the input voltage and the quiescent current are the lowest values in the published LDO's, which indicates the good energy efficiency of the digital LDO at 0.5-V operation.

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