This paper presents the design and implementation of 0.9-4.8GHz CMOS power amplifier (PA) with improved group delay variation and gain flatness at the same time for UWB transmitters. This PA design employs a two-stage cascade common source topology, a resistive shunt feedback technique and inductive peaking to achieve high gain flatness, and good input matching. Based on theoretical analysis, the main design factor for group delay variation is identified. The measurement results indicate that the proposed PA design has an average gain of 10.2 ± 0.8dB while maintaining a 3-dB bandwidth of 0.57 to 5.8GHz, an input return loss |S₁₁| less than -4.4dB, and an output return loss |S₂₂| less than -9.2dB over the frequency range of interest. The input 1dB compression point at 2GHz was -9dBm while consumes 30mW power from 1.5V supply voltage. Moreover, excellent phase linearity (i.e., group delay variation) of ±125ps was achieved across the whole band.