This paper introduces balanced switching schemes to compensate linear and quadratic gradient errors, in the unary current source array of a current-steering digital-to-analog converter (DAC). A novel algorithm is proposed to avoid the accumulation of gradient errors, yielding much less integral nonlinearities (INLs) than conventional switching schemes. Switching scheme examples with different number of current cells are also exhibited in this paper, including symmetric arrays and non-symmetric arrays in round and square outlines. (a) For symmetric arrays where each cell is divided into two parallel concentric ones, the simulated INL of the proposed round/square switching scheme is less than 25%/40% of conventional switching schemes, respectively. Such improvement is achieved by the cancelation of linear errors and the reduction of accumulated quadratic errors to near the absolute lower bound, using the proposed balanced algorithm. (b) For non-symmetric arrays, i.e. arrays where cells are not divided into parallel ones, linear errors cannot be canceled, and the accumulated INL varies with different quadratic error distribution centers. In this case, the proposed algorithm strictly controls the accumulation of quadratic gradient errors, and different from the algorithm in symmetric arrays, linear errors are also strictly controlled in two orthogonal directions simultaneously. Therefore, the INLs of the proposed non-symmetric switching schemes are less than 64% of conventional switching schemes.