Initialize and weak-program erasing scheme is proposed to achieve high-performance and high-reliability Ferroelectric (Fe-) NAND flash solid-state drive (SSD). Bit-by-bit erase V_TH control is achieved by the proposed erasing scheme and history effects in Fe-NAND is also suppressed. History effects change the future erase V_TH shift characteristics by the past program voltage. The proposed erasing scheme decreases V_TH shift variation due to history effects from ±40% to ±2% and the erase V_TH distribution width is reduced from over 0.4V to 0.045V. As a result, the read and V_PASS disturbance decrease by 42% and 37%, respectively. The proposed erasing scheme is immune to V_TH variations and voltage stress. The proposed erasing scheme also suppresses the power and bandwidth degradation of SSD.