A 580fs-Resolution Time-to-Digital Converter Utilizing Differential Pulse-Shrinking Buffer Ring in 0.18µm CMOS Technology

Tetsuya IIZUKA; Satoshi MIURA; Ryota YAMAMOTO; Yutaka CHIBA; Shunichi KUBO; Kunihiro ASADA

doi:10.1587/transele.E95.C.661

Special Section on Solid-State Circuit Design - Architecture, Circuit, Device and Design Methodology

A 580fs-Resolution Time-to-Digital Converter Utilizing Differential Pulse-Shrinking Buffer Ring in 0.18µm CMOS Technology

Tetsuya IIZUKA, Satoshi MIURA, Ryota YAMAMOTO, Yutaka CHIBA, Shunichi KUBO, Kunihiro ASADA

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Keywords: time-to-digital converter, pulse shrinking, buffer ring

JOURNAL RESTRICTED ACCESS

2012 Volume E95.C Issue 4 Pages 661-667

DOI https://doi.org/10.1587/transele.E95.C.661

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Abstract

This paper proposes a sub-ps resolution TDC utilizing a differential pulse-shrinking buffer ring. This scheme uses two differentially-operated pulse-shrinking inverters and the TDC resolution is finely controlled by the transistor size ratio between them. The proposed TDC realizes 9bit, 580fs resolution in a 0.18µm CMOS technology with 0.04mm² area, and achieves DNL and INL of +0.8/-0.8LSB and +4.3/-4.0LSB, respectively, without linearity calibration. A power dissipation at 1.5MS/s ranges from 10.8 to 12.6mW depending on the input time intervals.

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