In this paper, Source/Drain (S/i>/D) engineering for high performance (HP) Vertical MOSFET (V-MOSFET) in 3Xnm generation and its beyond is investigated, by using gradual S/i>/D profile while degradation of driving current (I_ON) due to the parasitic series resistance (R_para) is minimized through two-dimensional device simulation taking into account for gate-induced-drain-leakage (GIDL). In general, it is significant to reduce spreading resistance in the case of conventional Planar MOSFET. Therefore, in this study, we focused and analyzed the abruptness of diffusion layer that is still importance parameter in V-MOSFET. First, for improving the basic device performance such as subthreshold swing (SS), I_ON, and R_para, S/D engineering is investigated. The dependency of device performance on S/D abruptness (σ_S/D) for various Lightly Doped Drain Extension (LDD) abruptness (σ_LDD) is analyzed. In this study, Spacer Length (L_SP) is defined as a function of σ_S/D. As σ_S/D becomes smaller and S/D becomes more abrupt, L_SP becomes shorter. SS depends on the σ_S/D rather than the σ_LDD. I_ON has the peak value of 1750µA/µm at σ_S/D =2nm/dec. and σ_LDD=3nm/dec. when the silicon pillar diameter (D) is 30nm and the gate length (Lg) is 60nm. As σ_S/D becomes small, higher I_ON is obtained due to reduction of R_para while SS is degraded. However, when σ_S/D becomes too small in the short channel devices (Lg =60nm and Lg =45nm), I_ON is degraded because the leakage current due to GIDL is increased and reaches I_OFF limit of 100nA/µm. In addition, as σ_LDD becomes larger, larger I_ON is obtained in the case of Lg =100nm and Lg =60nm because channel length becomes shorter. On the other hand, in the case of Lg =45nm, as σ_LDD becomes larger, I_ON is degraded because short channel effect (SCE) becomes significant. Next, the dependency of the basic device performance on D is investigated. By slimming D from 30nm to 10nm, while SS is improved and approaches the ideal value of 60mV/Decade, I_ON is degraded due to increase of on-resistance (R_on). From these results, it is necessary to reduce R_para while I_OFF meets limit of 100nA/µm for designing S/D of HP V-MOSFET. Especially for the V-MOSFET in the 1Xnm generation and its beyond, the influence of the R_para and GIDL on I_ON becomes more significant, and therefore, the trade-off between σ_S/D and I_ON has a much greater impact on S/D engineering of V-MOSFET.