Data Convertors Design for Optimization of the DDPL Family

Song JIA; Li LIU; Xiayu LI; Fengfeng WU; Yuan WANG; Ganggang ZHANG

doi:10.1587/transele.E96.C.1195

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Data Convertors Design for Optimization of the DDPL Family

Song JIA, Li LIU, Xiayu LI, Fengfeng WU, Yuan WANG, Ganggang ZHANG

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Keywords: convertor, differential power analysis (DPA), information security, delay-based dual-rail precharge logic (DDPL), low power

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2013 Volume E96.C Issue 9 Pages 1195-1200

DOI https://doi.org/10.1587/transele.E96.C.1195

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Abstract

Information security has been seriously threatened by the differential power analysis (DPA). Delay-based dual-rail precharge logic (DDPL) is an effective solution to resist these attacks. However, conventional DDPL convertors have some shortcomings. In this paper, we propose improved convertor pairs based on dynamic logic and a sense amplifier (SA). Compared with the reference CMOS-to-DDPL convertor, our scheme could save 69% power consumption. As to the comparison of DDPL-to-CMOS convertor, the speed and power performances could be improved by 39% and 54%, respectively.

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