A Time-Domain Architecture and Design Method of High Speed A-to-D Converters with Standard Cells

Masao TAKAYAMA; Shiro DOSHO; Noriaki TAKEDA; Masaya MIYAHARA; Akira MATSUZAWA

doi:10.1587/transele.E96.C.813

Special Section on Analog Circuits and Related SoC Integration Technologies

A Time-Domain Architecture and Design Method of High Speed A-to-D Converters with Standard Cells

Masao TAKAYAMA, Shiro DOSHO, Noriaki TAKEDA, Masaya MIYAHARA, Akira MATSUZAWA

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Keywords: time-domain architecture, time-to-digital converter, interleaving, successive approximation

JOURNAL RESTRICTED ACCESS

2013 Volume E96.C Issue 6 Pages 813-819

DOI https://doi.org/10.1587/transele.E96.C.813

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Abstract

In this paper, we describe a new method to deal with analog signal in time domain. The method converts voltage signal to time-interleaved phase modulation signal of clock edge. After being amplified by a new time amplifier (TA), phases of the signal are converted to digital codes by successive approximation time-to-digital converter (SA-TDC). The test chip includes 8 interleaved 4bit SA-TDCs with short latency. The chip operates up to 4.4GHz. The measured ENOB is 3.51bit and FOM is 0.49pJ/conv.

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