A Low-Cost Stimulus Design for Linearity Test in SAR ADCs

An-Sheng CHAO; Cheng-Wu LIN; Hsin-Wen TING; Soon-Jyh CHANG

doi:10.1587/transele.E97.C.538

Special Section on Analog Circuits and Related SoC Integration Technologies

A Low-Cost Stimulus Design for Linearity Test in SAR ADCs

An-Sheng CHAO, Cheng-Wu LIN, Hsin-Wen TING, Soon-Jyh CHANG

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Keywords: analog-to-digital converter (ADC), design for testability (DFT), pattern generator (PG), output response analyzer (ORA)

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2014 Volume E97.C Issue 6 Pages 538-545

DOI https://doi.org/10.1587/transele.E97.C.538

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Abstract

The proposed stimulus design for linearity test is embedded in a differential successive approximation register analog-to-digital converter (SAR ADC), i.e. a design for testability (DFT). The proposed DFT is compatible to the pattern generator (PG) and output response analyzer (ORA) with the cost of 12.4-% area of the SAR ADC. The 10-bit SAR ADC prototype is verified in a 0.18-µm CMOS technology and the measured differential nonlinearity (DNL) error is between -0.386 and 0.281 LSB at 1-MS/s.

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