Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology
An On-Chip Monitoring Circuit with 51-Phase PLL-Based Frequency Synthesizer for 8-Gb/s ODR Single-Ended Signaling Integrity Analysis
Keywords:
on-chip monitoring circuit,
chip-to-chip interface,
analog-to-digital converter,
phase-locked loop-based frequency synthesizer,
sub-sampling
2016 Volume E99.C Issue 4 Pages 440-443
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