IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Online ISSN : 1745-1337
Print ISSN : 0916-8508
Special Section on VLSI Design and CAD Algorithms
A 197mW 70ms-Latency Full-HD 12-Channel Video-Processing SoC in 16nm CMOS for In-Vehicle Information Systems
Seiji MOCHIZUKI, Katsushige MATSUBARA, Keisuke MATSUMOTO, Chi Lan Phuong NGUYEN, Tetsuya SHIBAYAMA, Kenichi IWATA, Katsuya MIZUMOTO, Takahiro IRITA, Hirotaka HARA, Toshihiro HATTORI
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Keywords: video processing, automotive, low latency, memory-access-data compression
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2017 Volume E100.A Issue 12 Pages 2878-2887

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Abstract

A 197mW 70ms-latency Full-HD 12-channel video-processing SoC for in-vehicle information systems has been implemented in 16nm CMOS. The SoC integrates 17 video processors of 6 types to operate video processing independently of other processing in CPU/GPU. The synchronous scheme between the video processors achieves 70ms low-latency for driver assistance. The optimized implementation of lossy and lossless video-data compression reduces memory access data by half and power consumption by 20%.

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© 2017 The Institute of Electronics, Information and Communication Engineers
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