IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Online ISSN : 1745-1337
Print ISSN : 0916-8508
Regular Section
lq Sparsity Penalized STAP Algorithm with Sidelobe Canceler Architecture for Airborne Radar
Xiaoxia DAIWei XIAWenlong HE
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2017 Volume E100.A Issue 2 Pages 729-732

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Abstract

Much attention has recently been paid to sparsity-aware space-time adaptive processing (STAP) algorithms. The idea of sparsity-aware technology is commonly based on the convex l1-norm penalty. However, some works investigate the lq (0 < q < 1) penalty which induces more sparsity owing to its lack of convexity. We herein consider the design of an lq penalized STAP processor with a generalized sidelobe canceler (GSC) architecture. The lq cyclic descent (CD) algorithm is utilized with the least squares (LS) design criterion. It is validated through simulations that the lq penalized STAP processor outperforms the existing l1-based counterparts in both convergence speed and steady-state performance.

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© 2017 The Institute of Electronics, Information and Communication Engineers
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