IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Online ISSN : 1745-1337
Print ISSN : 0916-8508
Special Section on VLSI Design and CAD Algorithms
An Approach for Reducing Leakage Current Variation due to Manufacturing Variability
Tsuyoshi SAKATA, Takaaki OKUMURA, Atsushi KUROKAWA, Hidenari NAKASHIMA, Hiroo MASUDA, Takashi SATO, Masanori HASHIMOTO, Koutaro HACHIYA, Katsuhiro FURUKAWA, Masakazu TANAKA, Hiroshi TAKAFUJI, Toshiki KANAMOTO
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Keywords: low power, leakage, gate delay model, variation
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2009 Volume E92.A Issue 12 Pages 3016-3023

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Abstract

Leakage current is an important qualitative metric of LSI (Large Scale Integrated circuit). In this paper, we focus on reduction of leakage current variation under the process variation. Firstly, we derive a set of quadratic equations to evaluate delay and leakage current under the process variation. Using these equations, we discuss the cases of varying leakage current without degrading delay distribution and propose a procedure to reduce the leakage current variations. From the experiments, we show the proposed method effectively reduces the leakage current variation up to 50% at 90 percentile point of the distribution compared with the conventional design approach.

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© 2009 The Institute of Electronics, Information and Communication Engineers
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