IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Online ISSN : 1745-1337
Print ISSN : 0916-8508
Regular Section
A Study of Capture-Safe Test Generation Flow for At-Speed Testing
Kohei MIYASE, Xiaoqing WEN, Seiji KAJIHARA, Yuta YAMATO, Atsushi TAKASHIMA, Hiroshi FURUKAWA, Kenji NODA, Hideaki ITO, Kazumi HATAYAMA, Takashi AIKYO, Kewal K. SALUJA
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Keywords: at-speed scan testing, test generation, X-bit identification, X-filling, capture-safety checking
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2010 Volume E93.A Issue 7 Pages 1309-1318

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Abstract

Capture-safety, (defined as the avoidance of timing error due to unduly high launch switching activity in capture mode during at-speed scan testing), is critical in avoiding test induced yield loss. Although several sophisticated techniques are available for reducing capture IR-drop, there are few complete capture-safe test generation flows. This paper addresses the problem by proposing a novel and practical capture-safe test generation flow, featuring (1) a complete capture-safe test generation flow; (2) reliable capture-safety checking; and (3) effective capture-safety improvement by combining X-bit identification & X-filling with low launch-switching-activity test generation. The proposed flow minimizes test data inflation and is compatible with existing automatic test pattern generation (ATPG) flow. The techniques proposed in the flow achieve capture-safety without changing the circuit-under-test or the clocking scheme.

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© 2010 The Institute of Electronics, Information and Communication Engineers
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