A New LDMOS Transistor Macro-Modeling for Accurately Predicting Bias Dependence of Gate-Overlap Capacitance

Takashi SAITO; Toshiki KANAMOTO; Saiko KOBAYASHI; Nobuhiko GOTO; Takao SATO; Hitoshi SUGIHARA; Hiroo MASUDA

doi:10.1587/transfun.E93.A.1605

Regular Section

A New LDMOS Transistor Macro-Modeling for Accurately Predicting Bias Dependence of Gate-Overlap Capacitance

Takashi SAITO, Toshiki KANAMOTO, Saiko KOBAYASHI, Nobuhiko GOTO, Takao SATO, Hitoshi SUGIHARA, Hiroo MASUDA

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Keywords: LDMOS, macro model, gate-overlap capacitance, circuit simulation

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2010 Volume E93.A Issue 9 Pages 1605-1611

DOI https://doi.org/10.1587/transfun.E93.A.1605

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Abstract

We have developed a macro model, which allows us to describe precise LDMOS DC/AC characteristics. Characterization of anomalous gate input capacitance is the key issue in the LDMOS model development. We have newly employed a T-type distributed RC scheme for gate overlapped LDMOS drift region. The bias dependent resistance and capacitance are modeled independently in Verilog-A as R-model and PMOS-capacitance. The dividing factor of the distributed R is introduced to reflect the shield effect of the gate overlap capacitance. Comparison between the new model and measurement results has proven that the developed macro model reproduces accurately not only the gate input capacitance, but also DC characteristics.

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