IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Online ISSN : 1745-1337
Print ISSN : 0916-8508
Regular Section
Setup Time, Hold Time and Clock-to-Q Delay Computation under Dynamic Supply Noise
Takaaki OKUMURAMasanori HASHIMOTO
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2011 Volume E94.A Issue 10 Pages 1948-1953

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Abstract

This paper discusses how to cope with dynamic power supply noise in FF timing estimation. We first review the dependence of setup and hold times on supply voltage, and point out that setup time is more sensitive to supply voltage than hold time, and hold time at nominal voltage is reasonably pessimistic. We thus propose a procedure to estimate setup time and clock-to-Q delay taking into account given voltage drop waveforms using an equivalent DC voltage approach. Experimental results show that the proposed procedure estimates setup time and clock-to-Q delay fluctuations well with 5% and 3% errors on average.

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© 2011 The Institute of Electronics, Information and Communication Engineers
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