Substrate noise coupling has been seriously concerned in the design of advanced analog and radio frequency (RF) integrated circuits (ICs). This paper reviews recent advancements in the modeling, analysis, and evaluation of substrate noise coupling at IC chip level. Noise generation from digital circuits and propagation to the area of analog circuits are clearly visualized both by full-chip simulation as well as by on-chip measurements, for silicon test vehicles. The impacts of substrate noise coupling are also in-depth discussed at device, circuit, as well as system levels. Overall understanding of substrate noise coupling will then provide the basics for highly reliable design of analog and RF ICs.