A 24dB Gain 51-68GHz Common Source Low Noise Amplifier Using Asymmetric-Layout Transistors

Ning LI; Keigo BUNSEN; Naoki TAKAYAMA; Qinghong BU; Toshihide SUZUKI; Masaru SATO; Yoichi KAWANO; Tatsuya HIROSE; Kenichi OKADA; Akira MATSUZAWA

doi:10.1587/transfun.E95.A.498

Special Section on Analog Circuit Techniques and Related Topics

A 24dB Gain 51-68GHz Common Source Low Noise Amplifier Using Asymmetric-Layout Transistors

Ning LI, Keigo BUNSEN, Naoki TAKAYAMA, Qinghong BU, Toshihide SUZUKI, Masaru SATO, Yoichi KAWANO, Tatsuya HIROSE, Kenichi OKADA, Akira MATSUZAWA

Author information

Ning LI
Department of Physical Electronics, Graduate School of Science and Engineering, Tokyo Institute of Technology
Keigo BUNSEN
Department of Physical Electronics, Graduate School of Science and Engineering, Tokyo Institute of Technology
Naoki TAKAYAMA
Department of Physical Electronics, Graduate School of Science and Engineering, Tokyo Institute of Technology
Qinghong BU
Department of Physical Electronics, Graduate School of Science and Engineering, Tokyo Institute of Technology
Toshihide SUZUKI
Advanced Devices Lab., Fujitsu Laboratories Ltd.
Masaru SATO
Advanced Devices Lab., Fujitsu Laboratories Ltd.
Yoichi KAWANO
Advanced Devices Lab., Fujitsu Laboratories Ltd.
Tatsuya HIROSE
Advanced Devices Lab., Fujitsu Laboratories Ltd.
Kenichi OKADA
Department of Physical Electronics, Graduate School of Science and Engineering, Tokyo Institute of Technology
Akira MATSUZAWA
Department of Physical Electronics, Graduate School of Science and Engineering, Tokyo Institute of Technology

Keywords: asymmetric-layout, low noise amplifier, mm-Wave, 60GHz

JOURNAL RESTRICTED ACCESS

2012 Volume E95.A Issue 2 Pages 498-505

DOI https://doi.org/10.1587/transfun.E95.A.498

Details

Abstract

At mm-wave frequency, the layout of CMOS transistors has a larger effect on the device performance than ever before in low frequency. In this work, the distance between the gate and drain contact (D_gd) has been enlarged to obtain a better maximum available gain (MAG). By using the asymmetric-layout transistor, a 0.6dB MAG improvement is realized when D_gd changes from 60nm to 200nm. A four-stage common-source low noise amplifier is implemented in a 65nm CMOS process. A measured peak power gain of 24dB is achieved with a power dissipation of 30mW from a 1.2-V power supply. An 18dB variable gain is also realized by adjusting the bias voltage. The measured 3-dB bandwidth is about 17GHz from 51GHz to 68GHz, and noise figure (NF) is from 4.0dB to 7.6dB.

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