Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing

Hiroaki KONOURA; Dawood ALNAJJAR; Yukio MITSUYAMA; Hajime SHIMADA; Kazutoshi KOBAYASHI; Hiroyuki KANBARA; Hiroyuki OCHI; Takashi IMAGAWA; Kazutoshi WAKABAYASHI; Masanori HASHIMOTO; Takao ONOYE; Hidetoshi ONODERA

doi:10.1587/transfun.E97.A.2518

Special Section on VLSI Design and CAD Algorithms

Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing

Hiroaki KONOURA, Dawood ALNAJJAR, Yukio MITSUYAMA, Hajime SHIMADA, Kazutoshi KOBAYASHI, Hiroyuki KANBARA, Hiroyuki OCHI, Takashi IMAGAWA, Kazutoshi WAKABAYASHI, Masanori HASHIMOTO, Takao ONOYE, Hidetoshi ONODERA

Author information

Hiroaki KONOURA
Department of Information Systems Engineering, Osaka University
CREST, JST
Dawood ALNAJJAR
Department of Information Systems Engineering, Osaka University
CREST, JST
Yukio MITSUYAMA
CREST, JST
School of Systems Engineering, Kochi University of Technology
Hajime SHIMADA
CREST, JST
Information Technology Center, Nagoya University
Kazutoshi KOBAYASHI
CREST, JST
Graduate School of Science and Technology, Kyoto Institute of Technology
Hiroyuki KANBARA
CREST, JST
Advanced Scientific Technology & Management Research Institute of KYOTO
Hiroyuki OCHI
CREST, JST
Graduate School of Information Science and Engineering, Ritsumeikan University
Takashi IMAGAWA
Department of Communications and Computer Engineering, Kyoto University
Kazutoshi WAKABAYASHI
NEC Corporation
Masanori HASHIMOTO
Department of Information Systems Engineering, Osaka University
CREST, JST
Takao ONOYE
Department of Information Systems Engineering, Osaka University
CREST, JST
Hidetoshi ONODERA
CREST, JST
Department of Communications and Computer Engineering, Kyoto University

Keywords: reconfigurable architecture, soft error, radiation test, behavioral synthesis, state machine

JOURNAL RESTRICTED ACCESS

2014 Volume E97.A Issue 12 Pages 2518-2529

DOI https://doi.org/10.1587/transfun.E97.A.2518

Details

Abstract

This paper proposes a mixed-grained reconfigurable architecture consisting of fine-grained and coarse-grained fabrics, each of which can be configured for different levels of reliability depending on the reliability requirement of target applications, e.g. mission-critical applications to consumer products. Thanks to the fine-grained fabrics, the architecture can accommodate a state machine, which is indispensable for exploiting C-based behavioral synthesis to trade latency with resource usage through multi-step processing using dynamic reconfiguration. In implementing the architecture, the strategy of dynamic reconfiguration, the assignment of configuration storage and the number of implementable states are key factors that determine the achievable trade-off between used silicon area and latency. We thus split the configuration bits into two classes; state-wise configuration bits and state-invariant configuration bits for minimizing area overhead of configuration bit storage. Through a case study, we experimentally explore the appropriate number of implementable states. A proof-of-concept VLSI chip was fabricated in 65nm process. Measurement results show that applications on the chip can be working in a harsh radiation environment. Irradiation tests also show the correlation between the number of sensitive bits and the mean time to failure. Furthermore, the temporal error rate of an example application due to soft errors in the datapath was measured and demonstrated for reliability-aware mapping.

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