IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Online ISSN : 1745-1337
Print ISSN : 0916-8508
Special Section on Cryptography and Information Security
Unified Coprocessor Architecture for Secure Key Storage and Challenge-Response Authentication
Koichi SHIMIZUDaisuke SUZUKIToyohiro TSURUMARUTakeshi SUGAWARAMitsuru SHIOZAKITakeshi FUJINO
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2014 Volume E97.A Issue 1 Pages 264-274

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Abstract

In this paper we propose a unified coprocessor architecture that, by using a Glitch PUF and a block cipher, efficiently unifies necessary functions for secure key storage and challenge-response authentication. Based on the fact that a Glitch PUF uses a random logic for the purpose of generating glitches, the proposed architecture is designed around a block cipher circuit such that its round functions can be shared with a Glitch PUF as a random logic. As a concrete example, a circuit structure using a Glitch PUF and an AES circuit is presented, and evaluation results for its implementation on FPGA are provided. In addition, a physical random number generator using the same circuit is proposed. Evaluation results by the two major test suites for randomness, NIST SP 800-22 and Diehard, are provided, proving that the physical random number generator passes the test suites.

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© 2014 The Institute of Electronics, Information and Communication Engineers
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