135GHz 98mW 10Gbps CMOS Amplitude Shift Keying Transmitter and Receiver Chipset

Mizuki MOTOYOSHI; Naoko ONO; Kosuke KATAYAMA; Kyoya TAKANO; Minoru FUJISHIMA

doi:10.1587/transfun.E97.A.86

Special Section on Wideband Systems

135GHz 98mW 10Gbps CMOS Amplitude Shift Keying Transmitter and Receiver Chipset

Mizuki MOTOYOSHI, Naoko ONO, Kosuke KATAYAMA, Kyoya TAKANO, Minoru FUJISHIMA

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Keywords: CMOS, D-band, high-speed, wireless, ASK transceiver, short-millimeter-wave

JOURNAL RESTRICTED ACCESS

2014 Volume E97.A Issue 1 Pages 86-93

DOI https://doi.org/10.1587/transfun.E97.A.86

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Abstract

An amplitude shift keying transmitter and receiver chipset with low power consumption using 40nm CMOS technology for wireless communication systems is described, in which a maximum data rate of 10Gbps and power consumption of 98.4mW are obtained with a carrier frequency of 135GHz. A simple circuit and a modulation method to reduce power consumption are selected for the chipsets. To realize multi-gigabit wireless communication, the receiver is designed considering the group delay optimization. In the receiver design, the low-noise amplifier and detector are designed considering the total optimization of the gain and group delay in the millimeter-wave modulated signal region.

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