A Wide Bandwidth Analog Baseband Circuit for 60-GHz Proximity Wireless Communication Receiver in 65-nm CMOS

Masanori FURUTA; Hidenori OKUNI; Masahiro HOSOYA; Akihide SAI; Junya MATSUNO; Shigehito SAIGUSA; Tetsuro ITAKURA

doi:10.1587/transfun.E98.A.492

Special Section on Analog Circuit Techniques and Related Topics

A Wide Bandwidth Analog Baseband Circuit for 60-GHz Proximity Wireless Communication Receiver in 65-nm CMOS

Masanori FURUTA, Hidenori OKUNI, Masahiro HOSOYA, Akihide SAI, Junya MATSUNO, Shigehito SAIGUSA, Tetsuro ITAKURA

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Keywords: time-interleaved, SAR, ADC, dynamic, T/H circuit, high-speed, low-power

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2015 Volume E98.A Issue 2 Pages 492-499

DOI https://doi.org/10.1587/transfun.E98.A.492

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Abstract

This paper presents an analog front-end circuit for a 60-GHz proximity wireless communication receiver. The feature of the proposed analog front-end circuit is a bandwidth more than 1-GHz wide. To expand the bandwidth of a low-pass filter and a voltage gain amplifier, a technique to reduce the parasitic capacitance of a transconductance amplifier is proposed. Since the bandwidth is also limited by on-resistance of the ADC sampling switch, a switch separation technique for reduction of the on-resistance is also proposed. In a high-speed ADC, the SNDR is limited by the sampling jitter. The developed high resolution VCO auto tuning effectively reduces the jitter of PLL. The prototype is fabricated in 65nm CMOS. The analog front-end circuit achieves over 1-GHz bandwidth and 27.2-dB SNDR with 224mW Power consumption.

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