Abstract
Network-on-chip (NoC) communication architectures present promising solutions for scalable communication requests in large system-on-chip (SoC) designs. Intellectual property (IP) core assignment and mapping are two key steps in NoC design, significantly affecting the quality of NoC systems. Both are NP-hard problems, so it is necessary to apply intelligent algorithms. In this paper, we propose improved intelligent algorithms for NoC assignment and mapping to overcome the drawbacks of traditional intelligent algorithms. The aim of our proposed algorithms is to minimize power consumption, time, area, and load balance. This work involves multiple conflicting objectives, so we combine multiple objective optimization with intelligent algorithms. In addition, we design a fault-tolerant routing algorithm and take account of reliability using comprehensive performance indices. The proposed algorithms were implemented on embedded system synthesis benchmarks suite (E3S). Experimental results show the improved algorithms achieve good performance in NoC designs, with high reliability.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
Bjerregaard, T., Mahadevan, S., 2006. A survey of research and practices of network-on-chip. ACM Comput. Surv., 38(1):1.1–1.51. [doi:10.1145/1132952.1132953]
Cheng, A.L., Pan, Y., Yan, X.L., et al., 2011. A general communication performance evaluation model based on routing path decomposition. J. Zhejiang Univ.-Sci. C (Comput. & Electron.), 12(7):561–573. [doi:10.1631/jzus.C1000281]
da Silva, M.V.C., Nedjah, N., Mourelle, L.M., 2010. Power-aware multi-objective evolutionary optimisation for application mapping on network-on-chip platforms. Int. J. Electron., 97(10):1163–1179. [doi:10.1080/00207217.2010.512105]
Das, R., Eachempati, S., Mishra, A.K., et al., 2009. Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs. Proc. IEEE 15th Int. Symp. on High Performance Computer Architecture, p.175–186. [doi:10.1109/HPCA.2009.4798252]
Hu, J., Marculescu, R., 2003. Energy-aware mapping for tile-based NoC architectures under performance constraints. Proc. Asia and South Pacific Design Automation Conf., p.233–239. [doi:10.1109/ASPDAC.2003.1195022]
Hung, W.N.N., Song, X., 2001. BDD variable ordering by scatter search. Proc. Int. Conf. on Computer Design, p.368–373. [doi:10.1109/ICCD.2001.955053]
Jena, R.K., Sharma, G.K., 2007. A multi-objective evolutionary algorithm based optimization model for network-on-chip synthesis. Proc. 4th Int. Conf. on Information Technology, p.977–982. [doi:10.1109/ITNG.2007.10]
Liu, W., Gu, Z., Xu, J., et al., 2011. Satisfiability modulo graph theory for task mapping and scheduling on multiprocessor systems. IEEE Trans. Parall. Distr. Syst., 22(8):1382–1389. [doi:10.1109/TPDS.2010.204]
Marculescu, R., Ogras, U.Y., Peh, L.S., et al., 2009. Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst., 28(1):3–21. [doi:10.1109/TCAD.2008.2010691]
Masehian, E., Sedighizadeh, D., 2010. Multi-objective robot motion planning using a particle swarm optimization model. J. Zhejiang Univ.-Sci. C (Comput. & Electron.), 11(8):607–619. [doi:10.1631/jzus.C0910525]
Muralimanohar, N., Balasubramonian, R., Jouppi, N., 2007. Optimizing NUCA organizations and wiring alternatives for large caches with CACTI 6.0. Proc. 40th Annual IEEE/ACM Int. Symp. on Microarchitecture, p.3–14. [doi:10.1109/MICRO.2007.33]
Orgas, U.Y., Hu, J., Marculescu, R., 2005. Key research problems in NoC design: a holistic perspective. Proc. 3rd IEEE/ACM/IFIP Int. Conf. on Hardware/Software Codesign and System Synthesis, p.69–74. [doi:10.1145/1084834.1084856]
Rao, A.R.M., Arvind, N., 2005. A scatter search algorithm for stacking sequence optimisation of laminate composites. Compos. Struct., 70(4):383–402. [doi:10.1016/j.compstruct.2004.09.031]
Refan, F., Alemzadeh, H., Safari, S., et al., 2008. Reliability in application specific mesh-based NoC architectures. Proc. 14th IEEE Int. On-line Testing Symp., p.207–212. [doi:10.1109/IOLTS.2008.53]
Saxena, P.C., Gupta, S., Rai, J., 2003. A delay optimal coterie on the k-dimensional folded Petersen graph. J. Parall. Distr. Comput., 63(11):1026–1035. [doi:10.1016/S0743-7315(03)00116-3]
Sepulveda, M.J., Strum, M., Chau, W.J., 2011. A multi-objective adaptive immune algorithm for NoC mapping. Proc. 17th IFIP Int. Conf. on Very Large Scale Integration, p.193–196. [doi:10.1109/VLSISOC.2009.6041354]
Tang, L., Kumar, S., 2003. A two-step genetic algorithm for mapping task graphs to a network on chip architecture. Euromicro Symp. on Digital System Design, p.180–187. [doi:10.1109/DSD.2003.1231923]
Wang, J., Jiao, Y., Song, X., et al., 2012a. Optimal training sequences for indoor wireless optical communications. J. Opt., 14(1):015401.1–015401.5. [doi:10.1088/2040-8978/14/1/015401]
Wang, J., Xie, X., Jiao, Y., et al., 2012b. Optimal odd-periodic complementary sequences for diffuse wireless optical communications. Opt. Eng., 51(9):095002.1–095002.6. [doi:10.1117/1.OE.51.9.095002]
Yu, Q., Ampadu, P., 2010. A flexible parallel simulator for networks-on-chip with error control. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst., 29(1):103–116. [doi:10.1109/TCAD.2009.2034353]
Author information
Authors and Affiliations
Corresponding author
Additional information
Project supported by the National Natural Science Foundation of China (Nos. 60973016 and 61272175), the National Basic Research Program (973) of China (No. 2010CB328004), the Youth Backbone Teacher Foundation of Chengdu University of Technology (No. JXGG201305), and the Bagui Scholarship Project, China
Electronic supplementary materials: The online version of this article (http://dx.doi.org/10.1631/jzus.C1400055) contains supplementary materials, which are available to authorized users
Electronic supplementary material
Rights and permissions
About this article
Cite this article
Le, Qq., Yang, Gw., Hung, W.N.N. et al. Performance-driven assignment and mapping for reliable networks-on-chips. J. Zhejiang Univ. - Sci. C 15, 1009–1020 (2014). https://doi.org/10.1631/jzus.C1400055
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1631/jzus.C1400055