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Advancing source-level timing simulation using loop acceleration | IEEE Conference Publication | IEEE Xplore

Advancing source-level timing simulation using loop acceleration


Abstract:

Source-level timing simulation (STLS) is an important technique for early examination of timing behavior, as it is very fast and accurate. A factor occasionally more impo...Show More

Abstract:

Source-level timing simulation (STLS) is an important technique for early examination of timing behavior, as it is very fast and accurate. A factor occasionally more important than precision is simulation speed, especially in design space exploration or very early phases of development. Additionally, practices like rapid prototyping also benefit from high-performance timing simulation. Therefore, we propose to further reduce simulation run-time by utilizing a method called loop acceleration. Accelerating a loop in the context of SLTS means deriving the timing of a loop prior to simulation to increase simulation speed of that loop. We integrated this technique in our SLTS framework and conducted an comprehensive evaluation using the Malardalen benchmark suite. We were able to reduce simulation time by up to 43% of the original time, while the introduced accuracy loss did not exceed 8 percentage points.
Date of Conference: 19-23 March 2018
Date Added to IEEE Xplore: 23 April 2018
ISBN Information:
Electronic ISSN: 1558-1101
Conference Location: Dresden, Germany

References

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