Conventional ring oscillators are inherently prone to output frequency variation with the change of temperature and supply voltage. Various current starving techniques are used to control the current through the inverter delay stages in order to stabilize the output frequency. A simple current starved design with current mirrors and a PTAT bias generator can achieve total accuracy in the order of 10% across the temperature range from -40°C to 125°C. This paper presents a ring oscillator architecture with an improved biasing circuit, which improves the total accuracy of the output frequency to around 1% in the same temperature range. To achieve this result, the design uses a self-biasing scheme in combination with five differential output inverter delay stages. No additional circuitry is required for the manipulation of the control voltage. 200-MHz and 400-MHz variants of the oscillator are presented, each with two different implementations of the power-down mode. This makes a total of four different oscillator cores designed in 180-nm CMOS technology. The performance of the manufactured oscillators is evaluated, and measurement results are compared with simulations.