We propose a hybrid A/D converter consist of non-binary or beta-weighted cyclic ADC, and binary SAR ADC. The upper bits or MSBs are converted by beta-weighted cyclic ADC. With the help of automatic beta-value estimation, MSBs are converted accurately. One of the capacitors of the cyclic ADC is composed by a binary weighted capacitor array. After MSB conversion, residual voltage of cyclic ADC remains on the capacitor array. Lower bits or LSBs are determined using this capacitor array by Successive Approximation (SAR-) algorithm. Beta-weighted cyclic brings high accuracy to the ADC, and lower bit SAR-ADC helps to improve conversion speed and to reduce power consumption.