Abstract:
Over these last years, the number of cores witnessed a spectacular increase in digital signal and general use processors. Concurrently, significant researches are done to...Show MoreMetadata
Abstract:
Over these last years, the number of cores witnessed a spectacular increase in digital signal and general use processors. Concurrently, significant researches are done to get benefit from the high degree of parallelism. Indeed, these researches are focused to provide an efficient scheduling from hardware/software systems to multicores architecture. The scheduling process consists on statically choose one core to execute one task and to specify an execution order for the application tasks. In this paper, we describe an efficient scheduler that calculates the optimal number of cores required to schedule an application, gives a heuristic scheduling solution and evaluates its cost. Our proposal results are evaluated and compared with Preesm scheduler results and we prove that ours achieves better scheduling in terms of latency and number of cores.
Published in: 2017 25th International Conference on Software, Telecommunications and Computer Networks (SoftCOM)
Date of Conference: 21-23 September 2017
Date Added to IEEE Xplore: 23 November 2017
ISBN Information:
Electronic ISSN: 1847-358X