A 56Gb/s PAM-4 wireline receiver testchip is demonstrated in 7nm FinFET. The equalization is achieved with four stages continuous time linear equalizer (CTLE) and half-rate 10-tap decision feedback equalizer (DFE) with first tap speculative. Proposed voltage pre-shift scheme uses a programmable offset added on top of the differential data signal to alleviate front end nonlinearity. The receiver achieves BER <;1E-8 at optimal timing pre-FEC and 0.2UI at 1E-6 BER over 25dB insertion loss at 14GHz. The test-chip consumes 450mW under 1.0V/1.2V power supplies, giving a FoM of 0.321pJ/bit/dB. The active area is 0.352mm².