Abstract:
This paper presents an injection-locked PLL that employs RC pulse generator and injection timing calibration to enhance the jitter and reference spur performance. An ultr...View moreMetadata
Abstract:
This paper presents an injection-locked PLL that employs RC pulse generator and injection timing calibration to enhance the jitter and reference spur performance. An ultra-low power oscillator is designed to reduce the overall power consumption of the PLL. The chip is fabricated in 65nm CMOS technology, occupying an area of 0.25mm
2
. The proposed ILPLL achieves 70fs
rms
integrated jitter and -66dBc reference spur, while consuming 0.2mW, which translates into -270dB FoM at 2.4GHz output frequency.
Published in: 2019 Symposium on VLSI Circuits
Date of Conference: 09-14 June 2019
Date Added to IEEE Xplore: 29 July 2019
ISBN Information: