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0.2mW 70Fsrms-Jitter Injection-Locked PLL Using De-Sensitized SSPD-Based Injecting-Time Self-Alignment Achieving -270dB FoM and -66dBc Reference Spur | IEEE Conference Publication | IEEE Xplore

0.2mW 70Fsrms-Jitter Injection-Locked PLL Using De-Sensitized SSPD-Based Injecting-Time Self-Alignment Achieving -270dB FoM and -66dBc Reference Spur

Publisher: IEEE

Abstract:

This paper presents an injection-locked PLL that employs RC pulse generator and injection timing calibration to enhance the jitter and reference spur performance. An ultr...View more

Abstract:

This paper presents an injection-locked PLL that employs RC pulse generator and injection timing calibration to enhance the jitter and reference spur performance. An ultra-low power oscillator is designed to reduce the overall power consumption of the PLL. The chip is fabricated in 65nm CMOS technology, occupying an area of 0.25mm 2 . The proposed ILPLL achieves 70fs rms integrated jitter and -66dBc reference spur, while consuming 0.2mW, which translates into -270dB FoM at 2.4GHz output frequency.
Date of Conference: 09-14 June 2019
Date Added to IEEE Xplore: 29 July 2019
ISBN Information:

ISSN Information:

Publisher: IEEE
Conference Location: Kyoto, Japan

References

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