Abstract:
This work presents a high-density low bit error rate and low-power Mlink (MediaTek link) PHY for ultra-short-reach (USR) die-to-die communication. Proposed Mlink have bee...Show MoreMetadata
Abstract:
This work presents a high-density low bit error rate and low-power Mlink (MediaTek link) PHY for ultra-short-reach (USR) die-to-die communication. Proposed Mlink have been fabricated in TSMC 7nm FinFET 1P15M CMOS technology. Interconnection is demonstrated through TSMC Chip-on-Wafer-on-Substrate (CoWoS) and TSMC Integrated Fan-Out (InFO) packaging technology [1]. Mlink PHY exploits energy-efficient and high performance scheme, includes single-ended without termination, quarter rate strobe and unbalance scheme on transceiver, minimum intrinsic auto-alignment and novel noise-immunity coding methodology. Achieving 20Gb/s/wire and 0.46pJ/bit under 1-mm ultra-short-reach platform target to BER 1E-25. Bandwidth density is normalized with shoreline 5.31Tb/s/mm and area 2.25Tb/s/mm^2 respectively.
Published in: 2021 Symposium on VLSI Circuits
Date of Conference: 13-19 June 2021
Date Added to IEEE Xplore: 28 July 2021
ISBN Information: