Abstract:
This paper presents a body-biasing technique for an energy-efficient inverter-based integrator that significantly improves the PVT robustness of the integrators in sub-1V...Show MoreMetadata
Abstract:
This paper presents a body-biasing technique for an energy-efficient inverter-based integrator that significantly improves the PVT robustness of the integrators in sub-1V continuous-time delta-sigma modulators (CTDSMs). A prototype CTDSM with the body-biasing technique is implemented in a 28 nm CMOS process and achieves 83 dB SNDR, 84 dB SNR, and 86.5 dB DR in a 40-kHz bandwidth, while consuming only 33.6 μW from a 0.6 V supply. It achieves a Schreier FoM of 177.3 dB.
Published in: 2021 Symposium on VLSI Circuits
Date of Conference: 13-19 June 2021
Date Added to IEEE Xplore: 28 July 2021
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