In this paper we discuss the driving forces for moving to chip backside power delivery. Possible integration flows and challenges are discussed for integrating through-silicon via (TSV) connections that directly interconnect the chip at the standard-cell level. These approaches use power rail integration schemes that can be “buried” in the STI and Si below the devices or directly integrated as backside metallization scheme on the wafer backside. Both nTSV “last” and “first” integration flows have been demonstrated. Key technology challenges are the extreme wafer thinning required and back-side lithography correction to correct for wafer distortions caused by wafer processing and W2W bonding.