A 210 + WL layers 1Tb 3b/cell 3D-Flash Memory achieves the high bit density of $\gt17$ Gb/mm². Physical 8plane architecture realizes low read latency of 40us and high program throughput of 205MB. High interface speed of 3.2Gbps is accomplished by reducing DQ area in the X direction to 41%. Hybrid row address decoders (X-DEC) can deal with the wiring congestion issue caused by the new architecture, minimizing the read latency degradation. One-pulse-two-strobe technique reduces sensing time by 18% and contributes to the achievement of 205MB/s program throughput.