This paper presents a Digital Compute-In-Memory design in 12nm FinFET technology with capacity to store weights for 16 kernels per input channel. This macro is designed using an 8T SRAM push-rule foundry bitcell with integrated kernel selection and multiplication for an AI Edge application that achieves 30% better TOPS/mm² without loss of TOPS/W than a comparable logic-rule custom bitcell based architecture on the same silicon. We present novel power saving architectures, Activation Based Precharge and Folded Kernel Selector that achieves 11.2 TOPS/mm² and 137 TOPS/W with highest reported 16 kernels per input channel. Further, we showcase novel design circuitry to reduce peak current by 69.1% using a new Precharge During Write scheme.