Complementary FET (CFET) is a device architecture where n-and p-MOS transistors are stacked. As a result, the source and drain contact metals also need to be stacked. In this work, we tackle the high aspect-ratio (AR) patterning and metallization required for the monolithic CFET integration scheme. The bottom contact is formed by filling trenches with W up to AR =16 and CD =12 nm, followed by CMP and metal etch back at 45, 50 and 60 nm pitch printed by EUV lithography. We study the accuracy of the metal EB process using scatterometry, TEM and a new CDSEM technique, and observed a global Vertical Edge Placement Error (VEPE) as small as 2% for etch amounts ranging from 60 to 100 nm. Excellent correlation with electrical data was obtained. The top contact is separated from the bottom contact by an oxide fabricated in similar way (deposition, CMP and EB).