Addressing the major concern of area-inefficiency for metal-ferroelectricmetal-insulator-semiconductor (MFMIS) ferroelectric FETs (Fe-FETs), for the first time, we demonstrate 3D MFMIS Fe-FETs employing Multi-Fin floating gate (FG) that enlarges the channel area and realizes desired area ratio (AR) at a fixed device footprint. Such novel device architecture realizes an AR of 1:2.4 with$\sim$58.3% area saving as compared with the conventional planar structure. Together with the incorporation of an in-situ ALD deposited ferroelectric layer and TiN electrodes, as well as the ALD-enabled conformal growth of HfO2 dielectric layer and ZnO channel without breaking the vacuum for enhanced gate stack quality, the device with a channel length $(L_{\mathrm{C}\mathrm{H}})$ of 50 nm achieves a memory window (MW) of 1.5 V and endurance over $2\times 10^{9}$.