Abstract
This article continues a cycle of papers, which describe an approach to construction and verification of discrete PLC-programs by an LTL-specification. The approach provides a possibility of PLC-program correctness analysis by the model checking method. For the specification of the program behaviour the linear-time temporal logic LTL is used. The correctness analysis of an LTL specification is performed automatically by the symbolic model checking tool Cadence SMV. It was previously shown how ST-, LD- and IL-programs are constructed by a correct (with verified program properties) LTL-specification. In this article, a technology of CFC-program construction by an LTL-specification is described. The language CFC (Continuous Function Chart) is a variation of FBD (Function Block Diagram). FBD is a graphical language for microcircuits. CFC provides a possibility of free allocation of program components and connections on a screen. The approach to construction of CFC-programs is shown by an example. PLC-program representation on CFC within the approach to programming by LTLspecification differs from other representations. It gives the visualization of a data flow from inputs to outputs. The influence and dependence among variables is explicitly shown during the program execution within one PLC working cycle. In fact, CFC-program is a scheme of PLC-program data flow.
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Original Russian Text © D.A. Ryabukhin, E.V. Kuzmin, V.A. Sokolov, 2016, published in Modelirovanie i Analiz Informatsionnykh Sistem, 2016, Vol. 23, No. 2, pp. 173–184.
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Ryabukhin, D.A., Kuzmin, E.V. & Sokolov, V.A. Construction of CFC-Programs by LTL-Specification. Aut. Control Comp. Sci. 51, 567–575 (2017). https://doi.org/10.3103/S0146411617070173
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DOI: https://doi.org/10.3103/S0146411617070173