FPGA implementation of Spiking Neural Networks

https://doi.org/10.3182/20120403-3-DE-3010.00074Get rights and content

Abstract

Spiking Neural Networks (SNN) have optimal characteristics for hardware implementation. They can communicate among neurons using spikes, which in terms of logic resources, means a single bit, reducing the logic occupation in a device. Additionally, SNN are similar in performance compared to other neural Artificial Neural Network (ANN) architectures such as Multilayer Perceptron, and others. SNN are very similar to those found in the biological neural system, having weights and delays as adjustable parameters. This work describes the chosen models for the implemented SNN: Spike Response Model (SRM) and temporal coding is used. FPGA implementation using VHDL language is also described, detailing logic resources usage and speed of operation for a simple pattern recognition problem.

Keywords

neural network models
hardware synthesis
FPGA
VHDL
spiking neural network

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