Timing margin evaluation with a simple statistical timing analysis flow

Issue title: PATMOS 2007 selected papers on low power electronics

Article type: Research Article

Authors: Migairou, V. | Wilson, R. | Engels, S. | Wu, Z. | Azemard, N. | Maurine, P.

Affiliations: STMicroelectronics Design Department 850 rue J. Monnet, 38926, Crolles, France | LIRMM, UMR CNRS/Université de Montpellier II, (C5506), 161 rue Ada, 34392, Montpellier, France

Note: [] Corresponding author. E-mail: [email protected]

Abstract: The increase of within-die variations and the design margin growth are creating a need for statistical design methodologies. This paper proposes a simple statistical timing analysis method considering the lot to lot process shifts that occur during production. This method is validated for 90~nm and 65~nm process. Finally, this statistical timing analysis is applied to evaluate, on basic ring oscillators and combinational paths, the timing margins introduced at the design level by the traditional corner based approach.

Keywords: Statistical timing analysis, design margins

DOI: 10.3233/JEC-2009-0094

Journal: Journal of Embedded Computing, vol. 3, no. 3, pp. 221-229, 2009