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Synthesis of Analog Circuits by Genetic Algorithms and their Optimization by Particle Swarm Optimization

Synthesis of Analog Circuits by Genetic Algorithms and their Optimization by Particle Swarm Optimization

Esteban Tlelo-Cuautle, Ivick Guerra-Gómez, Carlos Alberto Reyes-García, Miguel Aurelio Duarte-Villaseñor
ISBN13: 9781605667980|ISBN10: 1605667986|ISBN13 Softcover: 9781616924164|EISBN13: 9781605667997
DOI: 10.4018/978-1-60566-798-0.ch008
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MLA

Tlelo-Cuautle, Esteban, et al. "Synthesis of Analog Circuits by Genetic Algorithms and their Optimization by Particle Swarm Optimization." Intelligent Systems for Automated Learning and Adaptation: Emerging Trends and Applications, edited by Raymond Chiong, IGI Global, 2010, pp. 173-192. https://doi.org/10.4018/978-1-60566-798-0.ch008

APA

Tlelo-Cuautle, E., Guerra-Gómez, I., Reyes-García, C. A., & Duarte-Villaseñor, M. A. (2010). Synthesis of Analog Circuits by Genetic Algorithms and their Optimization by Particle Swarm Optimization. In R. Chiong (Ed.), Intelligent Systems for Automated Learning and Adaptation: Emerging Trends and Applications (pp. 173-192). IGI Global. https://doi.org/10.4018/978-1-60566-798-0.ch008

Chicago

Tlelo-Cuautle, Esteban, et al. "Synthesis of Analog Circuits by Genetic Algorithms and their Optimization by Particle Swarm Optimization." In Intelligent Systems for Automated Learning and Adaptation: Emerging Trends and Applications, edited by Raymond Chiong, 173-192. Hershey, PA: IGI Global, 2010. https://doi.org/10.4018/978-1-60566-798-0.ch008

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Abstract

This chapter shows the application of particle swarm optimization (PSO) to size analog circuits which are synthesized by a genetic algorithm (GA) from nullor-based descriptions. First, a historical description of the development of automatic synthesis techniques to design analog circuits is presented. Then, the synthesis of analog circuits by applying a GA at the transistor level of abstraction is demonstrated. After that, the authors present the proposed multi-objective (MO) PSO algorithm which makes calls to the circuit simulator HSPICE to evaluate performances until optimal sizes of the transistors are found by using standard CMOS technology of 0.35µm of integrated circuits. Finally, the MO-PSO algorithm is compared with NSGA-II, and some open problems oriented to circuit synthesis and sizing are briefly discussed.

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