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90 nm CMOS Implementation of Multiplicative Inverse of the S-Box for AES Algorithm Using Six Transistor XOR Gate

90 nm CMOS Implementation of Multiplicative Inverse of the S-Box for AES Algorithm Using Six Transistor XOR Gate

Rithambara Shivraj Singh Rajput, Sujata Nandeshwar Patil
Copyright: © 2022 |Volume: 18 |Issue: 1 |Pages: 16
ISSN: 1548-3673|EISSN: 1548-3681|EISBN13: 9781799893868|DOI: 10.4018/IJeC.296684
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MLA

Rajput, Rithambara Shivraj Singh, and Sujata Nandeshwar Patil. "90 nm CMOS Implementation of Multiplicative Inverse of the S-Box for AES Algorithm Using Six Transistor XOR Gate." IJEC vol.18, no.1 2022: pp.1-16. http://doi.org/10.4018/IJeC.296684

APA

Rajput, R. S. & Patil, S. N. (2022). 90 nm CMOS Implementation of Multiplicative Inverse of the S-Box for AES Algorithm Using Six Transistor XOR Gate. International Journal of e-Collaboration (IJeC), 18(1), 1-16. http://doi.org/10.4018/IJeC.296684

Chicago

Rajput, Rithambara Shivraj Singh, and Sujata Nandeshwar Patil. "90 nm CMOS Implementation of Multiplicative Inverse of the S-Box for AES Algorithm Using Six Transistor XOR Gate," International Journal of e-Collaboration (IJeC) 18, no.1: 1-16. http://doi.org/10.4018/IJeC.296684

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Abstract

The Substitution-BOX is the most difficult architecture and is at the heart of any Advanced Encryption Standard algorithm implementation. It is the most complicated non-linear architecture using multiplicative inverse. It consumes maximum amount of the energy and power budget of the algorithm. This paper introduces a full-custom CMOS implementation of Multiplicative Inverse module for Substitution/ Inverse Substitution transformation in composite field arithmetic using Galois field GF (28). The multiplicative inversion module utilizes large number of XOR gates in its implementation. This paper introduces implementation of a novel XOR gate using six transistors. Using this six transistor XOR gate, the multiplicative inverse module is implemented in 90 nm CMOS technology. Simulation of the proposed design is achieved using Tanner EDA v.16 software. The area of the multiplicative inverse circuit is 39.92 µm2 requiring 776 transistors. With 0.6 Volts supply voltage, the design shows a power dissipation of 2.386 µWatts making it ideal for applications such as smart cards and RFID tags.

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