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Performance Optimization of Tridiagonal Matrix Algorithm [TDMA] on Multicore Architectures: Computational Framework and Mathematical Modelling

Performance Optimization of Tridiagonal Matrix Algorithm [TDMA] on Multicore Architectures: Computational Framework and Mathematical Modelling

Anishchandran Chathalingath, Arun Manoharan
Copyright: © 2019 |Volume: 11 |Issue: 4 |Pages: 12
ISSN: 1938-0259|EISSN: 1938-0267|EISBN13: 9781522564935|DOI: 10.4018/IJGHPC.2019100101
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MLA

Chathalingath, Anishchandran, and Arun Manoharan. "Performance Optimization of Tridiagonal Matrix Algorithm [TDMA] on Multicore Architectures: Computational Framework and Mathematical Modelling." IJGHPC vol.11, no.4 2019: pp.1-12. http://doi.org/10.4018/IJGHPC.2019100101

APA

Chathalingath, A. & Manoharan, A. (2019). Performance Optimization of Tridiagonal Matrix Algorithm [TDMA] on Multicore Architectures: Computational Framework and Mathematical Modelling. International Journal of Grid and High Performance Computing (IJGHPC), 11(4), 1-12. http://doi.org/10.4018/IJGHPC.2019100101

Chicago

Chathalingath, Anishchandran, and Arun Manoharan. "Performance Optimization of Tridiagonal Matrix Algorithm [TDMA] on Multicore Architectures: Computational Framework and Mathematical Modelling," International Journal of Grid and High Performance Computing (IJGHPC) 11, no.4: 1-12. http://doi.org/10.4018/IJGHPC.2019100101

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Abstract

Fast and efficient tridiagonal solvers are highly appreciated in scientific and engineering domain, but challenging optimization task for computer engineers. The state-of-the-art developments in multi-core computing paves the way to meet this challenge to an extent. The technical advances in multi-core computing provide opportunities to exploit lower levels of parallelism and concurrency for inherently sequential algorithms. In this article, the authors present an optimal performance pipelined parallel variant of the conventional Tridiagonal Matrix Algorithm (TDMA), aka the Thomas algorithm, on a multi-core CPU platform. The implementation, analysis and performance comparison of the proposed pipelined parallel TDMA and the conventional version are performed on an Intel SIMD multi-core architecture. The results are compared in terms of elapsed time, speedup, cache miss rate. For a system of ‘n' linear equations where n = 2^36 in presented pipelined parallel TDMA achieves speedup of 1.294X with a parallel efficiency of 43% initially and inclines towards linear speed up as the system grows.

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