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Performance Evaluation of SHA-3 Final Round Candidate Algorithms on ARM Cortex–M4 Processor

Performance Evaluation of SHA-3 Final Round Candidate Algorithms on ARM Cortex–M4 Processor

Rajeev Sobti, Geetha Ganesan
Copyright: © 2018 |Volume: 12 |Issue: 1 |Pages: 11
ISSN: 1930-1650|EISSN: 1930-1669|EISBN13: 9781522543060|DOI: 10.4018/IJISP.2018010106
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MLA

Sobti, Rajeev, and Geetha Ganesan. "Performance Evaluation of SHA-3 Final Round Candidate Algorithms on ARM Cortex–M4 Processor." IJISP vol.12, no.1 2018: pp.63-73. http://doi.org/10.4018/IJISP.2018010106

APA

Sobti, R. & Ganesan, G. (2018). Performance Evaluation of SHA-3 Final Round Candidate Algorithms on ARM Cortex–M4 Processor. International Journal of Information Security and Privacy (IJISP), 12(1), 63-73. http://doi.org/10.4018/IJISP.2018010106

Chicago

Sobti, Rajeev, and Geetha Ganesan. "Performance Evaluation of SHA-3 Final Round Candidate Algorithms on ARM Cortex–M4 Processor," International Journal of Information Security and Privacy (IJISP) 12, no.1: 63-73. http://doi.org/10.4018/IJISP.2018010106

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Abstract

SHA-3 was an open competition initiated by NIST to design new generation of hash functions. This competition was a necessity to overcome the challenges imposed by multiple attacks on MDx family of hash functions including SHA-0 and SHA-1. For this competition, NIST announced a reference platform which did not cover Embedded and Mobile machines. This paper compares the performance of SHA-3 final round candidate algorithms on ARM Cortex-M4 processor (embedded processor) and presents the results. Cycles per Byte is used as performance metric. Cortex-M4 based Stellaris® LM4F232 Evaluation Board (EK-LM4F232) from Texas Instruments is used for performance evaluation.

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